Power Electronics
Converter Synchronization Provides Design Flexibility

Converter Synchronization Provides Design Flexibility

Designs often require synchronization of two power converters within the same piece of equipment. Doing this fixes the noise at a particular frequency and eliminates the intermodulation effects. With the standard synchronization technique, the converter to be synchronized is designed to free-run at a lower than ideal frequency and then forced that unit to change state before its internal oscillator circuitry can call for the change. For several reasons, this method cannot always be used on some of the newer control chips.

A new method suitable for newer control ICs allows designers to synchronize one converter to another, while providing additional benefits. Using this synchronization technique, the synchronized converter is designed to operate at a desired nominal frequency, ignoring tolerances. Then, a signal fixed at that nominal frequency is used to adjust the converter's oscillator parameters to run at the desired frequency. This desired frequency may be another converter's natural running frequency, including its tolerances.

Standard Approach to Synchronization

Almost all existing converters use an internal ramp generator to set the frequency with two external components. The voltage ramp is generated by having a resistor from the chip's RT terminal to ground that sets a constant current into a capacitor connected between the CT terminal and ground. When the voltage ramp on the capacitor reaches a predetermined level, an internal comparator trips and discharges the capacitor. The most common method of synchronization has been to force the ramp voltage above the trip point at a frequency that corresponds to the synchronization frequency.

To ensure that a given converter will lock up, its internal voltage ramp must be designed such that the converter's highest frequency in the free-running state will be lower than the lowest frequency to which the unit is supposed to lock. In configuring the voltage ramp of the converter to be locked, designers must account for all the tolerances on the controller IC and its related components, which will influence that converter's switching frequency.

For example, imagine you have a PFC boost converter and a downstream converter, and you are locking to the downstream converter. Each converter has a ±15% tolerance on its switching frequency, requiring you to design the PFC to run at a natural frequency, nominally more than 30% below the downstream converter's nominal frequency.

When looking at the pulse required to lock the PFC converter, consider the opposite extreme. If, with tolerance, the PFC is free running at its low-end frequency (15% below its nominal frequency) and the downstream converter to which it is to be synchronized is running at its nominal frequency, then the PFC would free-run at 45% below the downstream converter's nominal frequency.

However, if the downstream converter is running fast, it has to pull the PFC to a frequency that is 15% above the nominal setting for the downstream converter. This means the PFC section's ramp amplitude will be about 35% of what the ramp would be if the PFC converter were running on its own. As a result, the pulse applied to the PFC's ramp has to be about 80% of the nominal ramp amplitude. This condition can result in significant loop-control problems from unit to unit.

For some of today's newer control circuits, the current method of synchronization is not available. And for various other reasons, it is desirable to have the ramp be a linear voltage with a fixed-voltage amplitude. For instance, the UCC38517 from Texas Instruments has an internal timing capacitor, so no pulse can be applied and a maximum duty-cycle clamp relies on a linear full-amplitude ramp voltage to set the duty-cycle limit.

A New Approach

Fig. 1 shows a new method that will result in the ramp's slope, not amplitude, changing so the two converters switch at the same frequency. With this technique, converters that have internal timing capacitors can be synchronized. In addition, special features such as programmable dead time, which use linearity of the ramp, now can be used with synchronization. Meanwhile, the dead time will remain a fixed percentage of the duty cycle, maintaining a maximum duty cycle independent of the converter's frequency.

The circuit in Fig. 1 requires two things to operate. The first is a pulse representing the frequency of the converter that is to be synchronized. This pulse is generated by U1A's output and converted into a negative going pulse by C1, R1 and D1. The second is a negative pulse representing the frequency to which the converter will be synchronized. This pulse is injected into pin 9 of the U1. These two signals are used to set and reset a flip-flop formed by U1b and U1c. Resistor R5 has been opened to generate a set of waveforms to show what voltages are developed in an unsynchronized condition (Fig. 2).

The flip-flop's buffered output on pin 11 of the IC is a PWM square wave occurring at the faster frequency of the two signals. It has a pulse width that is being phase modulated at the two signals' beat frequency, and that when put through a low-pass filter (R3/C3 and R4/C4) results in a saw-tooth waveform with a frequency equal to the difference between the two signals (Fig. 2 Trace 2).

In Fig. 2, the scope Trace 1 is the PWM control chip's internal ramp (obtained from CT-Buffer pin on the UCC28517 PFC/PWM controller). The combined effect of U1A and C1, R1 and D1 is the generation of a negative-going pulse on U1b pin 5 midway up this ramp's positive slope. Trace 3 is the incoming synchronization signal from the other converter. Trace 2 is the sawtooth signal that shows the averaged amplitude of the phase-shifting signal. This waveform is at a frequency equivalent to the difference between the frequency of the synchronization pulse and the frequency of the pulse generated from the converter's internal ramp. These waveforms were collected with R5 of Fig. 1 removed.

By connecting the filtered signal through a large value resistor (R5 in Fig. 1) to the RT chip's terminal, the current out of the UCC228517 controller chip can be either reduced or increased. Doing so can slow down or speed up the chip's running frequency. As the beat frequency changes, the voltage waveform on the output of the two-stage low-pass filter, capacitor (C4), changes. With the correct choice of polarity and component values, this voltage will approach a dc value as the two signals come into synchronization. This condition is shown in Fig. 3 where the converter is locked to the incoming synchronization signal's frequency.

In Fig. 3, Trace 1 is the UCC228517's ramp waveform, and Trace 3 is the incoming synchronization signal as it is in Fig. 2. Trace 2 is the filtered signal from the flip-flop at C4. This signal is injected into the RT pin on the UCC228517 controller. This was a 4 -V peak-to-peak waveform before the unit synchronized and is now about 0.88-V peak-to-peak. The two signals, Trace 1 and Trace 2, are synchronized. Looking at the ramp, Trace 1, it can be seen that it is a straight line with no pulse at the positive end to lock it in place.

Depending on the choice of components, the dynamic range over which synchronization can be achieved is quite extensive. Two examples shown below in Fig. 4 demonstrate the opposite extremes of the frequency, where synchronization is achieved and maintained for a particular set of components. In the two graphs in Fig. 4, Trace 2 is the IC's (U1-D) voltage on pin 11. Note that the voltage on pin 11 in Fig. 4a is high most of the time. This causes a high voltage to appear on C4, resulting in less current being drawn from the RT pin and hence a slower converter frequency. In Fig. 4b, the reverse is true where pin 11's (U1-D) voltage is generally low. This results in C4's voltage being low and more current being drawn from the RT pin, resulting in a higher frequency for the converter.

Notice that in both parts a and b of Fig. 4, the ramp (Trace 1) out of the controller chip is straight and of the same amplitude. This is a buffered ramp and represents the internal timing capacitor voltage ramp within the UCC28517. The slope, not the ramp amplitude, has changed to maintain the frequency. This means the gain equations will remain the same for voltage-controlled loops. It also means that the synchronization circuit will not affect any ancillary functions, such as duty-cycle limiting, which is available with this control circuit.

Choosing Component Values

Now consider the design of the synchronization circuit. The designer must establish the range of natural frequency for both the controlled converter and the incoming synchronization signal. The designer also must establish the voltage at the converters' RT pin to be synchronized.

From that information, the designer can establish the nominal current through the RT resistor and determine the amount of change in current out of the RT pin required to meet the frequency variations.

Next, look at the filtered-voltage dynamic range that will appear on the filter capacitor (C4) at the worst-case frequency difference. This is an ac signal passing through a low-pass filter. The filter rolloff will be set at a frequency at or above the maximum beat frequency. That is, if the synchronization frequency is 100 kHz and the converter tolerances indicates the converter could naturally operate between 80 kHz and 120 kHz, then the beat frequency could be as high as 20 kHz. If so, the filter should have a rolloff at or above 20 kHz, the extreme intermodulation or beat frequency.

Assume the maximum frequency to be the beat frequency and also assume a ramp waveform with an amplitude from zero to twice the voltage on the RT pin. Then determine the voltage to appear on the capacitor C4. From this information, the designer can determine the resistor's (R5) value to deliver or remove necessary current.

The flip-flop output should be capacitively coupled to the filter, so that a loss of signal from the synchronizing unit will not result in the converter's frequency shifting to one extreme or the other. The ac signal from the flip-flop (C2/R3 junction) should have an amplitude centered around the voltage on the RT pin so that the frequency can be either increased or decreased.

The synchronization circuit shows two low-pass filters to give a better high-frequency rolloff. This is not necessary, but will improve the ramp's linearity generated by the chip. The resistors used in these filters are added to R5 in determining the effective current to or from the RT pin.

A second representative circuit, Fig. 5, shows a circuit configuration for a UCC3808x PWM family where the timing capacitor is internal and its signal is inaccessible. In this case, the gate drives are used for the synchronization signal.

The circuit presented here allows the synchronization of a PWM converter while maintaining a linear ramp for circuits that utilize the ramp for other purposes. It also allows the synchronization of converters where the timing capacitor is not available. It further allows the converter to be synchronized to a signal that is either faster or slower than the converter's natural running frequency.

Another advantage of this circuit results from the phase shift between the sync signal and the converter's switching frequency. If multiple converters are running on the same dc power bus, various switches will turn on at different points in the cycle and will be distributed, rather than turning on all at the same time. This distributes the input current pulses over the full switching cycle.

For more information on this article, CIRCLE 333 on Reader Service Card

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.