Power Electronics

Bypass Capacitors for Point-of-Load Architecture

Distributed power architectures for advanced system designs have evolved to the point where cost-performance optimization is sensitive to the choice and location of load bypass capacitors.

Over the years, power electronics designers have witnessed two evolutions in power architectures. The first was the transition from centralized supplies to front-ends and “brick” converters. The second was the addition of another distribution layer to create the Intermediate Bus Architecture, an evolution driven by the “more and lower” phenomenon — the need for more voltage rails and lower voltages for today's microprocessors and fast-switching logic. Prior generations of DPA tended to be forgiving in these matters, but fast-transient POL (point-of-load) architectures require attention for optimal selection and placement of modern bypass capacitors.

The “more and lower” driver also pushes board designers to place the final stage of dc-dc conversion in close proximity to the load it feeds — in other words, at the “point-of-load.” In one critical area, the role of the POL converter designer and board-level system designer overlaps: the optimal choice of capacitors that result in the lowest system cost for a required level of performance. Hence, to maximize performance, the designer must know what types of capacitors to use and where to locate them.

Role of Capacitors

The changing role of the capacitor, as power architectures have evolved, is charted in Fig. 1. The amount of output capacitance on-board the converter has continued to decrease; and the capacitor type has changed as component technology and costs have changed. But first, given that the determination of the best choice of capacitors for a specific application requires an understanding of the load and converter characteristics, let's go back to the reasons why output capacitors are required in the first place — filtering and transient support. It's important to understand the inherent limitations of component technology, enabling the designer to compare the merits of various capacitor types.

The main role of the output capacitors in a switch-mode dc-dc converter is to provide an energy storage capability that smoothes out the output voltage in the presence of two sources of “disturbance.” The first disturbance is the pulsating flow of energy (periodic pulses) due to switching nature of the regulation. The second is the temporary imbalance between the output choke current and the load current that occurs during load steps or load transients.

Filtering Periodic Pulses

When switch-mode frequencies were in the 100kHz range, most capacitors could be modeled as an “ideal” capacitor (C) in series with an equivalent series resistance (ESR). Then, the action of the power switching resulted in triangle-like component of current in the output choke (L):

ΔIpeak-peak = Toff × (Vout+Vrect)/L

The voltage ripple calculation was simple:

ΔVpeak-peak = ΔIpeak-peak × ESR

In these cases, other than reducing the ESR, there was little that could be done to improve the performance of the power supply, but equally, little to make it worse.

However, most of today's dc-dc converters (in particular the multiphase type) switch at frequencies much higher than 100 kHz, making the task of minimizing voltage ripple and spikes more complex. First, you must take into consideration the capacitance (C) and equivalent series inductance (ESL). The ESR term in the previous equation must be substituted for the following impedance:

Zseries = ESR + j(2πf × ESL - 1/2πf×C)

This becomes more complex when parallel combinations of low-ESR capacitors are used to shape the transient response. Let's see what happens with the impedance of the output filter when ceramic capacitors are added to support tantalum capacitor.

In the case presented above, a low-impedance tantalum capacitor (1000µF, 5mΩ, 2.5nH) displays rising impedance above self resonant frequency (see the green curve in Fig. 2). The superimposed red curve represents total impedance of the output filter after adding 10µF of low impedance ceramic capacitors. These capacitors, while lowering the total impedance in frequencies above 1.5 MHz, actually make it worse around 1 MHz.

This is caused by the parallel resonance between the C of ceramics and ESL of the tantalum. If this resonance occurs near the frequency of the noise, the so-called “switching spikes” can be actually amplified by adding capacitors. This bizarre behavior explains itself if we observe the complex impedance of the parallel combination of capacitance (C) and “small inductance” (L) that might be introduced by layout impedance or larger size capacitor:

Zparallel = [(ESR - j/2πf × C) × j2πf × L]/ [(ESR - j/2πf × C + j2πf × L]

For small values of ESR, the denominator approaches zero at resonant frequency. As a result, the effective impedance tends toward infinity. In other words, if by adding more capacitors you happen to tune the parasitic resonant circuits in the layout, then you increase spikes instead of suppressing them.

Supporting Load Transients

A load transient (di/dt) is defined as a change in output current occurring over a defined period of time. Until the converter's control loop can “catch-up” with this event, the transient component of the load current is supplied by the output capacitor, either on-board the converter or on the system board. During the current excursion, voltage excursions are then dominated by the following terms:

V(t) = ESR × i(t) + ESL × di/dt

Minimization of voltage excursions under these conditions requires minimization of both ESR and ESL of the output capacitance. ESL goes with the capacitor geometry. Miniature SMT multilayer ceramic (MLC) capacitors have a low ESL and are favored for high-frequency applications. Substituting a 0508 part for a 0805 part further reduces ESL. Larger capacitors with higher ESL can be used to handle the slower components of the transient.

In exceptionally fast transient applications — powering today's microprocessors, for example — the problem is further complicated by the event having more than one important time constant. In these scenarios, parallel combinations of various capacitor types can be used, each targeting a different time-constant. Parallel combinations are difficult to analyze in closed-form, and a circuit simulator is usually required for design optimization.

Other system-level constraints have a bearing on the total capacitance and indirectly affect the theory. For example, consider applications where VOUT changes on the fly. Too much capacitance may prevent the ramping of voltage at the desired rate. Conversely, during converter “power-down,” too little capacitance can cause “backward resonance” of the output filter and creation of negative voltages — a danger to semiconductor loads. The larger the chokes and the smaller the capacitors, the larger this negative voltage will be.

Methodology for Placing Capacitors

Before proceeding with the basic methodology for selecting and placing the best combination of output capacitors for a POL dc-dc converter, it makes sense to review the general characteristics of available capacitors. The table, on page 38, summarizes the electrical, thermal, and mechanical characteristics, and embeds notes on reliability, aging, and cost.

When making a selection, verify environmental conditions and make sure that failure rate and life expectancy targets are met. In particular, check the lifetime of electrolytics in the target temperature range and realistic failure rate for ceramic capacitors (which are prone to cracking). When using large numbers of ceramics, particularly the larger sized, specify hi-rel types.

One starting point in the capacitor type selection process is to narrow the choice by locating the system design on the density-cost-frequency-efficiency axis depicted in Fig. 3.

The decision tree in Fig.4 can then be used as an aid to fine-tune the capacitor type best suited to a given constraint or environmental factor.

Since cost pressures always prevail, avoid chasing high frequency, high density targets if this is unjustified by necessity of achieving a compact size. There's no advantage in pursuing high-frequency ceramic capacitor designs except for the attainable high density, while the technical difficulties can be substantial:

  • lowered efficiency, more cooling
  • increased noise
  • more electrical, thermal stress
  • difficult compensation
  • elevated failure rate of numerous, high CV ceramics
  • single source, expensive controllers

At the same time, new and cheaper types of electrolytics offer performance levels that, until recently, were reserved for tantalums.

Stability and Transient Response

Next, evaluate the stability of the proposed solution and the associated transient response. A starting point might be the analysis tools provided by the converter's manufacturer. These can be used for a first-pass verification of the chosen capacitors. For example, the phase-margin contour plot of Fig. 5 can be used to choose an appropriate capacitor for a given stability requirement [1]. Alternatively, it can be used to verify stability for a given capacitor selection.

The next stage is an iterative process of verifying transient response, tweaking the design, and then reverifying stability. Usually, this is best accomplished using computer-based modeling and simulation tools: an example environment[2] is shown in Fig. 6, on page 45. Design of the loop compensation is based on well-known techniques that lend themselves to software applications: using one vendor's package[3] the user can “click-and-drag” the compensator poles and zeros on the Bode plot. In doing so, make sure the stability margins include the following:

  • Capacitor aging process (falling C, rising ESR)
  • Impact of remote sense leads connection (adds detrimental phase lag)
  • Thermal drifts
  • Switching noise

Other applications require more complex modeling techniques for the accurate selection of capacitors. For example, in the fast-transient application, there's an increased number of capacitive and inductive elements in the power distribution path. These may be parasitic elements or may be added intentionally. In such cases, closed-form modeling is usually impractical, and more advanced techniques, such as circuit simulation and/or mathematical modeling tools, are necessary. It's important to include ESL and ESR in capacitor models and any connector inductance. The inclusion of layout parasitics should also be considered.

In the iterative process, one goes between Bode plots and transient responses until both are satisfactory. For fast transients, include the inductance of the capacitors in your model, otherwise excessive inductive spikes will arise at the leading edge of the current wave. In the event of an inductive leading spike, supplement the capacitor bank with a certain number of smaller devices with lower ESL. The number of capacitors required should be within space/cost constraints. If space is at a premium, then increase the switching frequency and/or move to the next capacitor type on the left of Fig. 3, on page 40. If the cost is excessive, consider shifting to types on the left, accepting the increased size.

Physical Location

The interconnect between the converter and the POL represents a potential voltage drop during load transient events. The simplest method for overcoming these inductance effects is to shift the bulk of capacitance to the load side of the connector. Some high-frequency capacitance may be maintained for EMI reduction.

This in turn solves another potential problem. Significant inductance of the output connector can form a high-Q resonant circuit with the capacitors on the system side. As a result, if capacitors remain on the converter side of this connector, then this presents a 4th-order system, consisting of two LC filters: output choke and VRM capacitors, and output connector and system capacitors. This type of system can be difficult to compensate.

The presence of capacitors inside the VRM makes the transient performance worse in the 4th-order system. The only way out is to reduce or eliminate the capacitors inside the VRM, restoring the 2nd-order character of the output filter. The converter in Fig. 7 is an example of one where only EMI-capacitance exists between the output choke and connector.

Finally, carefully plan the board layout: use parallel plains for Vout and return to minimize L and R; avoid inductive loops; and place capacitors close to the load with the smallest devices nearest.

References

  1. Artesyn Technologies: www.artesyn.com
  2. SIMetrix Circuit Simulation Software: www.catena.uk.com/index.html
  3. Mathworks' MATLAB SISO Design Tool supports the interactive design of compensators for single-input/output linear systems: www.mathworks.com

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