Increased use of high-current brushless dc (BLDC) 3-phase motors puts stringent requirements on the drive electronics for function and safety. Answering the need to simplify motor drive design is a new 3-phase motor controller that integrates all the circuitry to control the six power NMOS FETs for fractional horsepower motors up to 50V.
The A3932 motor drive IC (Fig. 1) has three half-bridge drive circuits (only one is shown in the diagram). Each phase has a high- and low-side drive circuit providing the push-pull control to charge and discharge the external FET gates. The low-side gate driver runs off the regulated voltage VREG (13V with respect to ground), while the high-side driver circuit supply is bootstrapped above the motor supply Vbb.
To reduce slew rates, noise coupling, and emission problems, it is common practice to add resistors in series with the gates when driving high-current FETs in motor drive circuits. This technique increases turn-on and off times, so there is a danger that both FETs in a phase could be partially on at the same time during state changes. To prevent the resulting high shoot-through currents, the design provides a turn-on delay circuit that stops either driver from turning on until the other has been turned off for a fixed time. An external resistor on the DEAD pin sets this deadtime. It's up to the user to ensure this time is sufficient. An alternative scheme is to directly sense the gate voltage, allowing automatic crossover protection to be implemented. However, this would add six pins to the chip. This approach is not generally preferred by designers, because the deadtime scheme provides more flexibility.
The IC achieves PWM current control by chopping the high-side FET, which also guarantees frequent refresh of the bootstrap capacitor during normal operation. Also implemented is a fixed off-time control scheme where the user sets the scale (external sense resistor in the bridge's ground return) and the timing (parallel resistor/capacitor on the RC pin). You can use this fixed off-time function as the main current control loop or as an upper current limit with the PWM pin duty cycle providing the main control. To prevent false tripping by reverse recovery spikes, user-adjustable leading edge blanking is integral with this scheme.
Correct commutation of the three half-bridges requires accurate rotor position information. The standard way of doing this is with three Hall Effect sensors placed 120 electrical degree apart with their logic outputs being fed to the Hx inputs. You could also use any scheme that provides a clear logic level signal (such as angular position sensors or back-EMF detection).
The control logic block takes the commutation information and fixed off-time signal, with other user-controlled inputs (PWM, DIR, MODE, SR, BRAKE, and RESET), and decodes the appropriate logic states to all six outputs, as shown in Table 1.
Standard control functions of direction (DIR), pulse-width-modulation of the active high-side driver (PWM), RESET, and BRAKE are complemented by more advanced features — MODE and SR.
The MODE pin allows the selection of slow or fast decay modes, which defines the load current recirculation path during the off-time (Fig. 2), allowing the user flexibility to profile the load current waveform. During slow decay, only the high-side driver is turned off and the current recirculates through the same phase's low side. During fast decay, the same thing happens; however, the low-side driver is turned off so the current also recirculates through its partner high-side FET.
The SR input allows selection of synchronous rectification, which turns on the appropriate low- or high-side driver during recirculation and shorts out the reversed body diode, reducing power FET dissipation. The body diodes still conduct for the duration of the deadtime.
It's crucial for these types of high-current applications to have protection circuits to prevent inappropriate FET drive signals, as well as general circuit protection.
The process chosen for this device is ABCD3 (Allegro, Bipolar, CMOS, DMOS, 3rd generation). Merging analog bipolar/CMOS, low-voltage CMOS logic, and power DMOS transistors, ABCD3 features 65V vertical power DMOS as well as 12V, 35V, and 65V lateral DMOS transistors. In addition, it has several features that allow an efficient die size to be achieved for this design, such as the twin buried layers. One complication is the maximum on-chip gate-source voltage is restricted to 10V, so the design of several circuit blocks requires care to ensure no gates are overstressed — ABCD3 again helps, because there are suitable zener diode structures available for gate clamping. The device is assembled into a standard low-cost 32-lead PLCC package.
The requirements of the gate drive circuitry (especially the high-side driver) are very demanding:
- Provide an absolute minimum gate drive of 10V, for efficient power FET selection.
- Minimal static current consumption from the bootstrapped supply, which governs the size of the top-up charge pump.
- Operate from a 50V motor supply (VBB), which means up to 65V maximum on the bootstrapped supply nodes.
- Keep propagation delays low: target = 100 ns to 200 ns.
- Capable of driving 100 nC and higher FET gate charge.
These requirements, plus the other necessary circuit functions, must be integrated for as low a cost as possible, so silicon area is at a premium.
Fig. 3 shows the simplified circuit for the high-side driver. The bootstrapped supply, Vcs, is created by Cboot being charged from the 13V Vreg supply through diode d1 while the low-side power FET is on. Normally, during PWM operation (synchronous rectification ON and in slow decay mode) Cboot will charge up to:
Vcs = Vreg - Vfwd(d1) + Vds(low-side) (1)
Ensure the SENSE node doesn't show excessive negative transients due to stray inductance, because this could potentially lead to Vcs getting too high. The design approach adopted allows correct and safe operation — even with several volts negative on this node.
The gate of the external high-side FET is push-pull-driven through pin GH by transistors m1 and m2, which are sized for adequate drive levels (RDS(on) of 14Ω for the PMOS and 4Ω for the NMOS). To turn the high-side power FET on, m2 is driven on by current sink Ih2 fed through cascode transistor m7. Similarly, the high-side power FET is turned off by current sink Il2 fed through cascode m9, mirrored and fed into m1 gate, turning it on. As m1 and m2 are high gm devices and we must keep parasitic charge depletion of Cboot to a minimum, m1 and m2 must be prevented from being on at the same time during transitions. To do this the extra current sinks Ih1 and Il2 are switched in. For example, to turn on the high-side (m2 on), Ih1 starts to discharge m1's gate, but until this falls to a Vt, m3 and m4 remain on holding off the gate of m2 — once m3 turns off, m4 turns off and m2 can start to turn on, driven by Ih2. Similarly, for turn-off, m5 prevents Il2 from turning on m1 until m2 has virtually gone off. Ih1 and Il2 could have been derived from mirrors up at the bootstrap supply, but this would have added some extra consumption from Vcp and would have slowed down the transition time as the turn-off signal would have taken longer to propagate to the output.
We chose this technique over the pulsed high-side latch method  for two reasons:
- To ensure a steady state drive in case of noise transients that might cause loss of correct state.
- Maximum Vgs limitation makes gate clamping mandatory, which requires some current limiting (and hence current consumption) — leading naturally to a current-driven approach.
To keep current consumption from the bootstrapped supply to a minimum when the high-side driver is on, the current sinks are pulsed at 0.5mA for 1µs to allow sufficient time for all nodes to settle before falling back to a 2µA retention level. This gives a total static current consumption of about 10µA from the Cboot. The actual pulse time is made proportional to the user-selected dead time, so it can vary from around 0.3µs to 4µs, which provides slightly better matched drive duration.
The last but by no means trivial advantage of the bootstrap technique is in silicon area. Because most of the circuitry “floats” across Vcs (<15V) and the ABCD3 process has an N and P-type buried layer, low-voltage devices and layout can be used within an isolated epitaxial island tied to the C node — the spacings of the outer edge of the island must be high voltage, but this is only the periphery, so wastes little silicon area. Fig. 4, on page 25, shows a simplified cross-section. The current sources and switching circuits are all ground-referenced low voltage. Only the four cascode devices must be 65V lateral DMOS devices, and they are low-current signal devices (so they can be kept to minimum size). This gives an advantage over non-bootstrapped techniques.
Top-up Charge Pump
Under certain circumstances, the chip must maintain one phase state and keep the high-side drive on for long periods of time (100% duty cycle). Maintaining gate drive to the high-side FET is critical for these conditions. With no recharge cycles for the boot capacitor, the charge decay (and hence loss of gate drive) must be prevented. The high-side gate drive circuitry requires a small current drawn from the boot-capacitor; but even if this wasn't the case, there's no guarantee leakage on the Cx node (chip, board, and capacitor) wouldn't eventually create inadequate gate drive. Thus, it requires an auxiliary top-up circuitry.
Previous techniques  have used a high-side gate monitor circuit to force a boot capacitor recharge cycle whenever the gate voltage falls below a threshold. This system works well, but the intermittent loss of gate drive isn't usually desirable.
The method chosen for this chip is an internal low current top-up charge pump that is active when the high-side FET turns on (Fig. 5). In clock cycle Cb, the pump cap C1 is charged to -12V with respect to Vbb, set by the switched current sink I1 into R2 and clamped by Q1. In clock cycle C, switches S1 and S2 are opened and S3 closed — this pulls the bottom end of the capacitor to Vbb, reverse biases D1 and forward biases D2 passing charge to GH through M2. Regulating in the charge cycle avoids having to sense the voltage on the charge pump output (which can be as high as 62V nominal) and level shift a control signal back down. Pumping relative to Vbb avoids large and variable voltage swings on m1's drain and hence loss of charge due to parasitic capacitances on this node.
The presence of M2, M3, M4 and DZ1 allows the output to go below ground, which happens during output flyback. Due to the high-voltage operation of the charge pump, the pump diode D2 has a parasitic diode to substrate on its cathode, so this node can't go below ground. Once the output and D2 cathode have dropped below Vbb, M2 is switched off as its Vgs is negative. DZ1 clamps D2's cathode two diodes below Vbb and prevents negative transients to M2's gate. M3 and M4 ensure, during a normal pu mping cycle, no appreciable current leakage is through DZ1 to Vbb. This path would not turn on until Vz + 2Vthp (about 12.5V). The charge pump circuit is driven by a 1.8 MHz on-chip clock.
This chip implements a rigorous set of protection features to ensure that under almost any circumstance the FET drivers can be protected from fault conditions, poor set-up (e.g., deadtime too short), and situations that might limit the gate drive in some way, leading to excessive system power dissipation. Outputs are disabled if:
- The 13V regulated output falls below 9.1V, causing VREG UVLO (undervoltage lockout).
- Only six of the eight Hall states are valid positions; all 0s and all 1s are faults, which are invalid Hall states.
- Die temperature >165°C; re-enabled when die temperature cools 15°C.
- A short-to-ground on any phase node; detected if the S node does not get within 2V of Vbb when the high-side driver is turned on. This comparator is disabled until the high-side driver goes into its low-current drive state, to prevent false tripping as the drive settles. This fault is cleared at each phase commutation to allow limited operation even with one phase dead. However, if the fault causes the motor to stop before a commutation change, then a system reset will be required to clear the fault.
- Note that short-to-supply faults are effectively dealt with by the main current control loop.
- Inadequate charging of Cboot.
Ensuring that the bootstrap procedure is carried out correctly is one of the trickier of the implemented protection features. Monitoring the voltage across Cboot during charging and during use might seem ideal . However, a circuit implementation compatible with all the other operating requirements is non-trivial — especially the very low current consumption required while the high-side is on. So we adopted a three-way approach:
During Cboot charging, the charge current is monitored. The bootstrap charge path is about 9Ω, so Cboot is not considered to be charged until this current has dropped to around 9mA. This means it will be guaranteed to be charged to about 100 mV from the maximum.
The bottom end of Cboot (i.e., the S node) is monitored to ensure it is less than 1V from ground.
Time-out: if conditions 1 and 2 are not met within 60µs, then there must be a fault preventing Cboot from charging. To prevent excessive power dissipation and/or VREG failure, the Cboot charging path is disconnected. Reset or commutation is required to clear this.
The combination of the above conditions (plus the VREG UVLO) ensures the high-side is only turned on if Cboot is fully charged. If not, the phase is disabled and made safe. The only lack of direct protection in this scheme is the lack of monitor of the high-side gate drive voltage. However, this is covered indirectly by the “short-to-ground” detector. If the FET starts to lose gate drive, its Vds will increase and be detected by the high-side “short-to-ground” monitor.
Allegro Microsystems Inc. A3933 datasheet.
High-voltage integrated circuits for off-line power applications by C. Diazzi (Chapter 8 of Smart Power Applications; B. Murari, F. Bertotti, and G. A. Vignola [Eds]; Springer 1996).
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