Power Electronics

The Road Ahead for Power Electronics

The 2009 Issue of the International Technical Roadmap for Semiconductors contains the latest projections of semiconductor technology. It is jointly sponsored by European Semiconductor Industry Association (ESIA), Japan Electronics and Information Technology Industries Association (JEITA), Korea Semiconductor Industry Association (KSIA), Taiwan Semiconductor Industry Association (TSIA), and Semiconductor Industry Association (SIA) in the U.S. The following is included in the overview to the 2009 ITRS. From a power electronics viewpoint, the important part of this report is the projected operating voltages and power for the future.

For more than four decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in its products. Most of these trends have resulted principally from the industry's ability to exponentially decrease the minimum feature sizes used to fabricate integrated circuits. Of course, the most frequently cited trend is in integration level, which is usually expressed as Moore's Law (that is, the number of components per chip doubles roughly every 24 months). The most significant trend is the decreasing cost-per-function, which has led to significant improvements in economic productivity and overall quality of life through proliferation of computers, communication, and other industrial and consumer electronics.

POWER SUPPLY AND POWER DISSIPATION

The reduction of power supply voltage is driven by several factors — reduction of power dissipation, reduced transistor channel length, and reliability of gate dielectrics. Selection of a specific Vdd value continues to be a part of the analysis undertaken to simultaneously optimize speed and power for an IC, leading to a range of usable power supply voltages in each product generation. Values of Vdd as low as 0.6 volts are not expected to be achieved by high-performance processors until 2024. The lowest Vdd target is still 0.6V in 2021 for the low operating power applications, and is not expected to drop below that level out to 2024.

Maximum power trends (e.g., for MPUs) are presented in three categories — 1) high-performance desktop applications, for which a heat sink on the package is permitted; 2) cost-performance, where economical power management solutions of the highest performance are most important; and 3) portable battery operations. In all cases, total power consumption targets are relatively flat in the 2009 Table 1, despite the use of a lower supply voltage. The power consumption is driven by higher chip operating frequencies; the higher interconnect overall capacitance and resistance, and the increasing gate leakage of on-chip transistors.

The reduction of power supply voltage is driven by several factors — reduced power dissipation, reduced transistor channel length, and reliability of gate dielectrics. As seen in Table 1, the value of the power supply voltage is now given as specific target, rather than a range.

Selection of a specific Vdd value continues to be a part of the analysis undertaken to simultaneously optimize speed and power for an IC. Vdd values as low as 0.6 volts are not expected to be achieved by high-performance processors until 2024. The lowest projected Vdd target, 0.6V in 2021, is not expected to drop below that level until 2024.

POWER SUPPLY VOLTAGE (VDD)
Application 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024
High Performance 0.97 0.93 0.90 0.87 0.84 0.81 0.78 0.76 0.73 0.71 0.68 0.66 0.64 0.62 0.60
Low Operating Power 0.95 0.85 0.85 0.80 0.80 0.75 0.75 0.70 0.70 0.65 0.65 0.60 0.60 0.60 0.60
ALLOWABLE MAXIMUM POWER (W)
High-Performance with Heat Sink 146 161 158 149 152 143 130 130 136 133 130 130 130 ------ ------
Maximum Affordable MPU Chip Size 260 260 260 260 260 260 260 260 260 260 260 260 260 260 260
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