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Traditional power factor corrected designs utilize a boost topology to accomplish the input power factor correction (PFC) function. The boost topology results in a nonisolated, high-voltage (approximately 400-V) dc output. This high-voltage output powers a dc-dc converter, which provides the required output voltages and input-to-output isolation.
Many new integrated circuits are being developed for the purpose of PFC control. Some of these new controllers incorporate both the PFC controller and a dc-dc controller within a single chip, while others offer critical-mode (also called transition-mode) control. The critical conduction mode eases the reverse-recovery stress that is seen by the boost diode.
The boost topology offers several benefits, primarily a very high operating efficiency. Because the boost converter only has to switch the difference between the input voltage and the output voltage, this topology generally results in small magnetic elements and efficiencies higher than 95%, with the voltage being somewhat proportional to the input voltage.
The boost topology also has some negatives such as the inability to short-circuit protect the boost stage. Another drawback is the high stress on the boost diode that results from very high dV/dT at a high applied voltage during the reverse-recovery period. The boost topology also exhibits a large inrush current unless an inrush limiter circuit is included, which adds to the complexity of the design. Additionally, the boost topology generally requires a dc-dc converter, which in turn requires the power to be switched twice and pushes up the parts count because of the two stages.
In many applications, it is preferable to perform the PFC and the isolation within a single converter stage. This is presently common in low-power applications up to about 40 W using SEPIC and discontinuous-conduction-mode flyback topologies. Four topologies may be used to provide a 28-V, 200-W output from a single-phase 400-Hz input. The four topologies include the critical-conduction isolated SEPIC, the continuous-conduction isolated SEPIC, the single-phase voltage-mode flyback and the multiphase (two-, three- or four-phase) voltage-mode flyback.
While all four of these converter topologies can accommodate a universal input range, the major considerations for this article are overall operating efficiency, fundamental input conducted emissions, output capacitor stress, reliability and relative cost. Table 1 summarizes the key performance criteria. The performance of each of the topologies is assessed at a nominal 115-VRMS, 400-Hz input voltage. The values shown in the table are from calculation or PSPICE simulation. EMA Design Automation supplied the PSPICE software and Power IC Model Library used for the simulation (www.EMA-EDA.com).
While the performance of the critical conduction boost is outstanding, it still needs an isolated dc-dc converter, which consumes watts and dollars, losing much if not all of its advantage. The SEPIC topology was interesting, but with simple control circuitry, it results in relatively high distortion and also the output capacitor ripple current is very high. The ripple current is significant because the output capacitors are expensive and have high failure rates. Topologies that reduce the number of output capacitors required or the output ripple current are advantageous for that reason.
Taking all of these requirements into account, we chose one of the four topologies as the basis for the detailed single-stage PFC converter design discussed in this article. A prototype of this design was built and evaluated for performance. Cornell Dubilier Capacitors (www.cde.com) assisted with the design and supplied the high ripple-current, low-ESR capacitors. Champs Technologies (www.champs-tech.com) provided detailed magnetics designs and samples for the prototypes.
The topology selected for this application is the two-phase voltage-mode flyback. The multiphase flyback offers lower RMS currents in the input and output by effectively increasing the duty cycle. The schematic used for PSPICE simulation of the topology is shown in Fig. 1, while simulation results are shown in Figs. 2 and 3.
The two-phase voltage-mode flyback offers a significant ripple current reduction in the output capacitor, high efficiency and reasonable cost. The four-phase solution might be more attractive at higher power levels and there are three- and four-phase buck controllers available, but such a design appears overly complex for the 200-W power level.
The discontinuous-mode flyback naturally provides PFC using standard voltage-mode control circuits. The peak primary current (IP) of the flyback, along with the expected efficiency, can be calculated as follows:
where VIN is the input voltage applied at the top of the power transformer (rectified sine wave), LP is the primary inductance and TON is the on-time of the MOSFET. The power delivered to the load is:
where Freq is the switching frequency. Substituting for IP and substituting for PIN gives the input resistance.
Therefore, it can be seen that for a fixed primary inductance, fixed on-time and fixed frequency, the input appears resistive. If LP = 80 µH, TON = 4.5 µsec and Freq = 100 kHz, then RIN = 79.012 Ω. This relationship determines the maximum power available at minimum load. The equation for RIN also clearly shows that if TON, LP and Freq are all constant, then the input resistance is constant, defining PFC. The distortion is then based primarily on the errors (variations) in LP, TON and Freq within a cycle.
For POUT = 200 W, VIN = 115 VRMS and VOUT = 28 V:
If the efficiency is assumed to be 90%, then η=0.9 and PIN=222.222 W. The average current then becomes:
or IIN(0.004333) = 2.195 A.
If we assume that there are N phases, then the input power is split evenly between each of the N phases. If N = 2, then:
and PN×2 = 0.5 LPI2PKsw×Freq.
For LPRI = N×40×10-6 and Freq = 100×103 Hz,
which gives IPKsw = 7.538 A and
Duty = TON, Freq = 0.371. The RMS inductor current can be estimated as:
Assessing the MOSFET switch losses with TC = 50×10-9 s and RDS(ON) = 0.4 Ω.
giving PFETsw = 3.065 W.
The conduction losses are defined by:
PFETcond = I2FETrms×RDS(ON)×N, where PFETcond = 2.809 W.
The input rectifier losses are a result of the forward voltage, VF in, and the input current, VF in = 0.88 V:
and the output rectifier loss is VF out = 0.85 V:
PXFMR = POUT×2.656%.
The transformer leakage inductance losses are also dissipated. With a measured leakage inductance of 1.5 µH, the leakage power is calculated as follows:
LLEAKAGE = 0.75×10-6×N
PLOSS = 28.875 W
Efficiency = 0.874.
The design approach for an isolated flyback transformer for PFC is similar to a discontinuous-mode (DCM) flyback transformer. The difference is that, for the PFC application, the input voltage and current vary more than one-half of the cycle of the ac input.
Optimizing the transformer requires an accurate computation of the winding and core losses. The method shown in reference 3 computes the Fourier components of the voltage waveform (across the primary) and then computes the core loss for each harmonic of the waveform. The core loss curves and equations supplied by most core manufacturers are for sine wave excitation, making this an ideal method. Similarly, the Fourier components of the current waveforms for the primary and secondary are derived and the winding losses for each harmonic are then computed. This allows a formulaic approach using skin and proximity effects to accurately predict the winding losses. Most traditional methods for DCM do not go into this level of detail because a first-order approach is often satisfactory.
Design equations must be written and the analytical results compared to empirical data on efficiency and temperature rise. In our two-phase example, each transformer provides half the output power, or 100 W with a switching frequency of 100 kHz. Consequently, LP = 80×10-6 H, IPKpri = 7.5 A, IPRIrms = 2.6 A, transformer turns ratio = 0.25 and ISECrms = 7.65 A.
Two transformer design choices were selected for evaluation: a PQ2620 size ferrite core and a standard PL58 size planar ferrite core. Both transformers were constructed. Results of the PQ calculations are shown in Table 2. The leakage inductance of the transformer was measured to be 1.5 µH at 100 kHz. A relative cost comparison of the two choices is also shown.
The PQ core finds worldwide usage currently in existing off-line ac-dc power supplies resulting in a very low cost. The planar cost is directly related to the number of boards or layers (lead frame or pc board) required to achieve the design requirements. Applications more amenable to planar designs usually occupy niches in telecom, “bricks,” servers and high current/power. The result is that the PQ core is substantially less expensive than the planar counterpart, due to the high production volume of the part. For that reason, this article concentrates on the PQ design, though both were built for evaluation.
The first planar design resulted in very high leakage inductance. Additional work will be done to improve the leakage inductance so that the planar can be properly evaluated. The planar design has the benefits of very low profile and very low labor cost.
Fig. 4 shows the actual schematic for the two-phase voltage-mode flyback design that was constructed. The design utilized a National Semiconductor LM5033, 100-V push-pull voltage-mode pulse-width modulated (PWM) controller. This controller was selected for several reasons. It has low initial operating current and up to 100-V input. It also provides high-current output drivers and a wide operating temperature range. A final benefit is that it is designed for applications using optically coupled feedback.
The reliability of the supply is almost totally dependent on the output capacitor. The failure rate of the output capacitor is, in turn, dramatically affected by the ripple current. For the selected CDE capacitor, failure rates vary from more than 100,000 hours to under 10,000 hours as the ripple current goes from 0% of the rated value to 150% of the rated value.
The math for the capacitor ripple current shows the theoretical minimum current for the line frequency component, which is what we would get if we had an infinite number of stages (no high-frequency contribution):
POUT = 200 W and VOUT = 28 V
The current in the output capacitor at the line frequency is:
ICAP(t) = IPK×sin(t)-IOUT
and the RMS capacitor current at the line frequency is:
= 3.453 A.
Of course, in addition to this current, there is also the high-frequency switching component; however, this is the minimum theoretical limit.
As the number of phases is increased, the capacitor ripple current will decrease asymptotically toward this theoretical minimum. Table 3 shows the mean-time-before-failure (MTBF) calculations for one-, two-, three- and four-phase versions of the flyback supply.
In the two- and three-phase versions, two capacitors were required. The number of capacitors must be sufficient to handle the output capacitor ripple current, with adequate derating to improve the reliability. While the four-phase approach would further reduce the number of output capacitors, it was decided that the two-phase solution was adequate for this power level. The four-phase solution would require a more elaborate — and expensive — control circuit.
Since the output capacitor is also the most expensive component and almost solely responsible for the MTBF, its failure rate is more than 500 times that of any other component in the system, the number of phases must be carefully assessed for each application.
Fig. 5 shows the input voltage and current waveforms. A Voltech PM100 power analyzer and Elgar model 1001B were used in the testing of the two-phase flyback supply. The power analyzer is accurate to 0.1% for voltage, 0.1% for current, 0.2% for power and 0.4% for THD. The Elgar distortion limit is 0.6%, making it hard to measure the expected 1% distortion.
The measured performance for the final converter design is in excellent agreement with the calculated and simulated results. Table 4 lists the measured and calculated values for converter performance using the PQ2620 transformers. Additional refinements of the power transformer may be feasible. The mathematical models having been proven out can now be used to evaluate specific design solutions using the multiphase flyback topology.
Sandler, Steven M. Switchmode Power Supply Simulation with PSPICE and SPICE 3, McGraw-Hill, 2006, ISBN 0-07-146326-7.
PSPICE Power IC Model Library Documentation, AEi Systems LLC, 2005.
“Magnetic Core Calculations for 200W 28V Multi-Phase Flyback,” www.AENG.com/Articles/Flyback.asp.
|Critical Conduction Boost*||Critical Conduction Isolated SEPIC||Continuous Conduction Isolated SEPIC||Voltage-Mode Flyback||Two-Phase Voltage-Mode Flyback||Four-Phase Voltage-Mode Flyback|
|Emissions||170 mA at 106 kHz||247 mA at 100 kHz||667 mA at 50 kHz||1.69 A at 100 kHz||0.826 A at 200 kHz||0.233 A at 400 kHz|
|Ripple Current||1.108 ARMS||12.30 ARMS||11.3 ARMS||13.6 ARMS||8.09 ARMS||6.07 ARMS|
|* Still required a dc-dc converter for isolation.|
|Core||Width (mm)||Length (mm)||Height (mm)||Core Area (mm2)||Volume (mm3)|
|Core||Secondary Cu Loss (W)||Gap Loss (W)||Core Loss (W)||AC Loss (W)||Total Loss (W)|
|Core||Cost per 1000 units||Cost per 10,000 units||Cost per 50,000 units||Cost per 100,000 units||Cost per 1,000,000+ units|
|Number of Phases||Output Caps Utilized||Ripple per Cap (ARMS)||Failure Rate for Output Caps (fpmh)||Unit Failure Rate (fpmh)||Unit MTBF (hr)|