In most power-supply design examples it is common to arbitrarily place the crossover frequency at one-fifth or one-tenth the switching frequency. However, the crossover frequency actually affects the converter's output impedance and there is a true relationship between these two parameters. Therefore, once a designer selects the output capacitor based on its operating parameters such as rms current, temperature or acceptable voltage ripple, the designer can analytically select the crossover frequency to match the desired output undershoot.
This discussion shows how to derive the relationship that links crossover frequency and undershoot and describes how to tailor the bandwidth to fit exactly the converter's design requirements.
Simplified Buck Converter
Fig. 1 shows a simplified buck converter represented by a square-wave generator driving a low-pass filter. Both the inductor and the capacitor have ohmic losses. The output impedance of such a network can be derived with the input source shorted:
where ZOUT equals the output impedance in ohms, LOUT equals the output inductance in henrys, COUT equals the output capacitance in farads, rLf equals the inductor resistance in ohms and rCf equals the COUT equivalent series resistance (ESR) in ohms.
Through inspection, the designer can see that the inductor's resistance dominates the output impedance at dc (LOUT is shorted and COUT is open) and that its inductance dominates as the frequency increases. Then the capacitor impedance starts to take over until it becomes a short circuit and leaves the impedance value to its series loss rCf.
By connecting a 1-A ac source to the output, the designer has the ability to quickly plot the output impedance versus frequency using a SPICE simulator. Fig. 2 portrays the obtained results. As can be seen, a peaking occurs at the resonant frequency (f0). The maximum of this peaking can be analytically derived:
where ZOUTMAX equals the maximum output impedance in ohms and Z0 = equals the characteristic impedance of the filter in ohms.
Such peaking is typical of a buck output impedance behavior where the LC filter has been optimized to minimize the losses. This situation induces a high-quality coefficient, hence a severe peaking in the impedance graph. One of the feedback aims is to minimize the output impedance to reduce as much as possible the voltage drop due to a load step. On an amplitude versus frequency plot, the natural output impedance of the filter dramatically peaks at the resonant frequency. Therefore, if a crossover frequency below the LC filter resonance is selected, there will not be enough of a gain to get rid of the resonance and, despite a good phase margin, the system will oscillate. If the designer wants to obtain a good transient response, he or she has to make sure the loop gain remains high enough to tame the peaking when it occurs. In other words, the crossover frequency (fC) must be selected at least three to five times above f0.
In Fig. 2, if a crossover region is selected beyond the resonance, the designer can see an impedance graph dominated by the output capacitor impedance (COUT). At the crossover frequency, this impedance is:
where fC equals the crossover frequency and ZOUTOL equals the open-loop output impedance.
Above the crossover frequency, the capacitor's ohmic losses dominate the network's output impedance. To ensure Eq. 3 rules the output impedance alone at the crossover point, the capacitor ESR must be much smaller than the output impedance at the crossover frequency. Mathematically, the following condition must be met:
In choosing the final capacitor, besides ripple current and temperature considerations, the designer must also consider the capacitor ESR at the selected crossover frequency.
Closing the Loop
Picture any voltage generator with an equivalent circuit associating a dc source VTH and an output resistor RTH. According to Thévenin's theorem, VTH is evaluated by measuring the output voltage on an unloaded converter and RTH is found by measuring the output-voltage difference in two loading current conditions. Imagine that Fig. 3a depicts an open-loop buck converter using the Fig. 1 approach. Once loop control is installed through a compensator, bringing gain and phase boost as in Fig. 3b, the open-loop impedance transforms into a closed-loop output impedance that now obeys Eq. 5 (Fig. 3c):
where ZOUTCL (s) equals closed-loop output impedance for a loop gain of T(s) = H(s)G(s).
The designer now has an output impedance whose value depends on the open-loop gain. At dc, for s = 0, assume a large loop gain to ensure good dc regulation. In other words, the feedback brings the open-loop impedance to a very low value. On the contrary, when the frequency increases, the gain reduces and when the crossover point is reached, the gain no longer acts upon the output impedance. Mathematically, this is:
If a SPICE average model is used and a voltage-mode buck converter is compensated, there is the possibility to ac sweep its output impedance as was done in Fig. 2. The output impedance in Fig. 4 shows what Eqs. 5 and 6 predicted: Thanks to a high open-loop gain in the low-frequency domain, the output impedance remains extremely small, . But as the frequency increases, inductive behavior can start to be seen. Then, at the crossover point, the loop gain reaches 0 dB and both the open-loop and closed-loop impedances are almost equal to the output capacitor impedance given by Eq. 3.
Approximate Output Impedance
Previously, the term “almost” has been used to compare the open- and closed-loop output impedances at the crossover frequency. However, try to see how close they are in the vicinity of the crossover point. There are several methods to calculate the module of Eq. 5's right term, . One method applies a sinusoidal modulation to the complete chain made of the converter transfer function H(s) followed by the compensator transfer function G(s).
This is exactly what would be done in the laboratory to explore the true open-loop response of the compensated converter. However, in this particular case, rather than expressing the modulation signal through a classical form of sin(wt+j), a phasor notation will be used where φ represents the phase lag brought by the total chain when stimulated at the crossover frequency. Following is what details for a 1-V modulation.
The phasor notation can be update using Euler's formula:
In this equation, the term φ relates to the phase difference between the output signal and the input modulation. A design criteria here is not φ but jm, the phase margin. To help link both, Fig. 5 shows the contribution of the loop to the total phase lag.
Based on the figure, it can be written:
Solving for j, we have:
Based on Eq. 10, Eq. 8 can be updated as:
Knowing that the loop gain module at crossover is 1, T(s) can be approximated as:
Based on this result, Eq. 5 can now be updated as:
Solving this equation yields:
As can be seen, the module of the capacitor impedance is now affected by a term dependent on the phase margin. The variations of this term can now be plotted versus the phase margin as proposed by Fig. 6.
As observed, a phase margin below 60 degrees degrades the converter's output impedance, whereas it slightly improves it for a phase margin above 60 degrees.
Assuming a power supply with an output capacitor of 1000 µF, the designer needs to make a choice considering the output-voltage ripple conditions and the corresponding rms current circulating in the capacitor. The specification here notes that there should be a maximum voltage drop of 80 mV when the converter undergoes a current step ΔIOUT of 2 A. What bandwidth is needed to reach this parameter? If Eq. 3 is used and a 2-A step is applied, the voltage drop can be predicted:
From this equation, it is easy to extract the minimum crossover point:
Based on this result, the designer must check that the capacitor ESR is lower than:
A 1000-µF capacitor from the Panasonic FM series could be the right choice. From the manufacturer's data sheet, the capacitor has an ESR of 19 mΩ at 100 kHz. This ESR alone will contribute to a drop of 19 × 10-3 × 2 = 38 mV, which is 47% of the specification. To offer some margin in this design, increase the crossover frequency to 6 kHz and purposely compensate the converter to meet this goal.
Once compensated, the 5-V voltage-mode buck converter loop-gain Bode plot SPICE simulation appears in Fig. 7. It shows a crossover frequency of 5.8 kHz together with a rather comfortable phase margin of 76 degrees. The output-voltage drop is now going to split between the capacitor and its ESR term. Based on a 76 degree phase margin, the capacitive contribution can be approximated using Eq. 14:
Now step load the output by a current source ranging from 100 mA to 2.1 A in 10 µs (Fig. 9). Fig. 8 shows the simulation results. It can be seen that the total output undershoot is well within the design goals with a theoretical 53.5-mV deviation. The ESR spike is 35 mV and lasts only during the output-current circulation in the capacitor. The capacitive contribution reaches 50 mV, which is a fairly good agreement with the Eq. 14 predictions.
As can be seen, the ESR term amplitude depends on the output-current step. When the load change is slow enough, the loop has a means to attenuate the ESR contribution. However, usually the transient loading conditions are so fast that all the current step translates into a voltage spike over the ESR. Given its steepness, the loop cannot fight it.
The situation degrades further if the output-current rate of change reaches high values, like in motherboard applications for instance. In that case, the inductive term called the capacitor's equivalent series inductance (ESL) starts to enter the picture and the situation worsens. In these extreme cases, the capacitor selection is almost solely based on the contribution of its parasitic terms and no longer on its capacitive value.
Therefore, the designer can analytically select a crossover frequency rather than arbitrarily choosing it based on the switching frequency. If the capacitor impedance plays a role in relationship with the selected crossover frequency, there are other terms whose contribution is out of control, such as the ESR and ESL of the output capacitor. They are respectively sensitive to the output-current step and the current slope. As loop control has almost no influence on their contributions, it is the designer's task to make sure these parasitic terms stay low enough to keep the overall transient response within the original specifications.
- Basso, Christophe, Switch Mode Power Supplies: SPICE Simulations and Practical Designs, McGraw-Hill, 2008.